This invention relates generally to semi-conductor devices, and more particularly to a packaging system for providing as a single unitary component multiple semi-conductor devices.
With the increasing complexity and miniaturization of present day electronic apparatus an increasing demand has developed for densely packaged integrated circuit devices. This demand has exceeded the ability of semi-conductor manufacturers to deliver specific monolithic solutions, thus creating a pressing need for a packaging system whereby a number of integrated circuit devices can be interconnected in a single component package. The present invention is directed to a packaging system which meets this requirement and combines a plurality of individual integrated circuit devices in a single unitary component which is mechanically compatible with previous generations of semi-conductor packages to take advantage of existing automatic manufacturing and assembly techniques.
Various techniques for the interconnection of individual semi-conductor devices in high density applications have been developed. One technique, which is described in U.S. Pat. No. 3,564,114, utilizes laminated multi-layer printed circuit boards for interconnecting individually packaged devices. Another technique, which is described by H. D. Kaiser et al. in an article entitled "A Fabrication Technique for Multi-Layer Ceramic Modules", Solid State Technoloov. May 1972, pages 35-40, utilizes multi-layer ceramic substrates capable of interconnecting either packaged or unpackaged semi-conductor devices on a single substrate.
These two techniques have been used to produce a number of different types of semi-conductor packages which provide increased packing density on a given parent circuit board. An example of one such package is a single in-line package (SIP) consisting of a small daughter substrate upon which several individually packaged semi-conductors are mounted. The daughter substrate has either an array of metal fingers soldered onto one side or a card edge connector for connection to the parent substrate/circuit board. The daughter substrate thus projects up perpendicular to the plane of the parent substrate and is connected on only one side.
Another example is the dual in-line package (DIP), which comprises a small multi-layer substrate upon which several packaged or unpackaged semi-conductor devices are mounted. An array of metallic fingers is soldered or brazed to the edge of the substrate and arranged so that the fingers extend at right angles to the substrate to make mechanical and electrical connections to an underlying parent substrate. The daughter substrate is thus parallel to the parent substrate and is connected on two or more sides. A variation of this construction is described in U.S. Pat. No. 4,322,778.
These packaging constructions provide at least two advantages as a result of packing more functionality into a given size package. Firstly, a sma11er parent substrate is required to serve a given function. Secondly, the length of the interconnects between individual devices is reduced, resulting in the ability to derive higher performance from the resulting module.
The present invention improves on these constructions by providing a unitary component package of appreciably higher circuit density, which package is of standard configuration for mechanical compatibility with existing circuit constructions.